An E cient Architecture for Loop Based Data Preloading

Cache prefetching with the assistance of an optimizing compiler is an e ective means of reducing the penalty of long memory access time beyond the primary cache. However, cache prefetching can cause cache pollution and its bene t can be unpredictable. A new architectural support for preloading, the preload bu er, is proposed in this paper. Unlike previously proposed methods of nonbinding cache loads, the preload is a binding access to the memory system. The preload bu er is simple in design and predictable in performance. With simple interleaving, accesses to the preload bu er are independent of the access pattern and processor issue rate, and are therefore free of bank con icts. With trace driven simulation, it is shown that the performance from preloading hides memory latency better than no prefetching and cache prefetching. In addition, both the bus tra c rate and the miss rate are reduced.